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GM16C550 1 GM16C550 asynchronous communications element with fifos descriptions the GM16C550 is an asynchronous communi - cations element (ace) that is functionally equivalent to the gm16c450, and addition - ally incorporates a 16byte fifos are available on both the transmitter and receiver, and can be activated by placing the device in the fifo mode. after a reset, the registers of the GM16C550 are identical to those of the gm16c450. the uart performs serial - to - parallel conver - sion on data characters received from a peri - pheral device or a modem, and parallel - to - serial c onversion on data characters received from the cpu. the cpu can read the com - plete status of the uart at any time during the functional operation. status information reported includes the type and condition of the transfer operations being perform ed by the uart, as well as any error conditions (parity, overrun, framing, or break interrupt). pin configulation features l fully compatible with gm16c450. l modem controm signals include cts , rts , dsr , dtr , ri and - dcd . l programmable serial characteristics: ? 5 - , 6 - , 7 - or 8 - bit characters ? even - , odd - , or no - parity bit generation and detection ? 1 - , 1 1/2 - or 2 - s top bit generation ? baud rate generation (dc to 256k baud) l 16 byte fifo reduces cpu interrupts. l independent control of transmit, receive, line status, data set interrupts, fifos. l full status reporting capabilities l three - state, ttl drive capabilities for bi - derectional data bus and control bus. l 40dip/44plcc d0 d1 d2 d3 d4 d5 d6 d7 rclk sin sout cs0 cs1 cs2 baudqut xtal1 xtal2 dostr dostr vss vcc ri dcd dsr cts mr out1 dtr rts out2 intrpt rxrdy a0 a1 a2 ads distr distr ddis txrdy d 6 d5 d7 rclk sin n.c. sout cs0 cs1 cs2 baudqut a1 a2 a0 rxrdy intrpt n.c. out2 rts dtr out1 mr d1 d2 d3 d4 d0 n.c. vcc ri dcd dsr cts vss n.c. distr distr ddis txrdy
GM16C550 2 absolute maximum ratings temperature under bias c 0 to + c 70 storage temperature c 65 - to + c 150 all input or output voltages with respect to ss v v 5 . 0 - to + v 0 . 7 power dissipation 500 mw note : maximum ratings indicates limits beyond which permanent damage may occur. continuous opera - tion at these limits is not intended and should be limited to those conditions specified under dc electrical characteristics. dc electrical characteristics c 0 a t = to + c 70 , % 5 v 5 cc v = , v 0 ss v = unless otherwise specified symbol parameter min max units conditions ilx v clock input low voltage - 0.5 0.8 v ihx v clock input high voltage 2.0 cc v v il v input low voltage - 0.5 0.8 v ih v input high voltage 2.2 cc v v ol v output lo w voltage 0.4 v 6 . 1 i ol = ma on all, note 1 oh v output high voltage 2.4 v 0 . 1 i oh - = ma , note 1 ) av ( i cc average power supply current( cc v ) 10 (note 2) ma cc v =5.25 v , no loads on output sin dsr, dcd, cts il i input leakage 10 a m cl i clock leakage 10 a m cc v =5.25 v , ss v =0 v . all other pins floating. v 0 v in = , 5.25 v oz i 3 - state leakage 20 a m cc v =5.25 v , gnd =0 v . v 0 v out = ,5.25 v 1) chip deselected 2) write mode, chip selected ilmr v mr schmitt il v 0.8 v ihmr v mr schmitt ih v 2.2 v note 1 . does not apply to xout. note 2. ta=25c capitance c 25 t a = , v 0 v v ss cc = = symbol parameter min tye max units conditions xin c clock input capitance 15 20 pf mhz 1 f c = xout c cl ock output capitance 20 30 pf unmeasured pins in c input capitance 6 10 pf returned to ss v out c output capitance 10 20 pf
GM16C550 3 ac characteristics c 0 t a = to v 5 v , c 70 cc = + 5% symbol parameter min max units conditions ads t address srobe width 60 ns ah t address hold time 0 ns ar t rd , rd delay from address 30 ns note 1 as t address setup time 60 ns aw t wr , wr delay from select 30 ns note 1 ch t chip select hold time 0 ns cs t chip select setup time 60 ns csr t rd , rd delay from chip select 30 ns note 1 csw t wr , wr delay from select 30 ns note 1 dh t data hold time 30 ns ds t date setup time 30 ns hz t rd , rd to floating data delay 0 100 ns 100 pf loading, note 3 mr t master reset pulse width 5 ns ra r address hold time from rd , rd 20 ns note 1 rc t read cycle delay 125 ns rcs t chip select hold time from rd , rd 20 ns note 1 rd t rd , rd strobe width 125 ns rdd t rd , rd to driver enabl e/disable 60 ns 100 pf loading, note 3 rvd t delay from - rd , rd to data 125 ns 100 pf loading, wa t address hold time from wr , wr 20 ns note 1 wc t write cycle delay 150 ns wca t chip select hold time from wr , wr 20 ns note 1 wr t wr , wr strobe width 100 ns xh t duration of clock high pulse 55 ns external clock (8.0 mhz max.) xl t duration of clock low pulse 55 ns exrternal clock (8.9 mhz max.) rc read cycle= rc rd ar t t t + + 280 ns note 4 wc write cycle= wc wr aw t t t + + 280 ns baud generator n baud divisor 1 16 2 - 1 bhd t baud output positive edge delay 175 ns 100 pf load bld t baud output negative edge delay 175 ns 100 pf load hw t baud output up time 75 ns mhz 0 . 8 f x = , +2, 100 pf load lw t baud output down time 100 ns mhz 0 . 8 f x = , +2, 100 pf load
GM16C550 4 ac characteristics c 0 t a = to c 70 + , % 5 v 5 v cc = symbol parameter min max units conditions receiver rint t delay from rd , rd (rd rbr/ or rd lsr) to reset interupt 1 s m 100 pf load scd t delay from rclk to sample time 2 s m sint t delay from stop t o set interrupt 1 rclk cycles note 2 transmitter hr t delay from wr , wr (wr thr) to reset interrupt 175 ns 100 pf load ir t delay from rd , rd (rd iir) to reset interrupt (thre) 25 0 ns 100 pf load irs t delay from initial intr reset to transmit start 8 24 baudout cycles si t delay from initial write to interrupt 16 24 baudout cycles note 5 sti t delay from stop to interrupt (thre) 8 8 baudout cycles note 5 sxv t delay from start to txrdy active 8 baudout cycles 100 pf load wxi t delay from write to txrdy inactive 195 ns 100 pf load modem control mdo t delay from wr , wr (wr mcr) to output 200 ns 100 pf load rim t delay to reset interrupt from rd , rd (rd msr) 250 ns 100 pf load sim t delay to set interrupt from modem input 250 ns 100 pf load no tes 1. applicable only when ads is tied low. 2. in the fifo mode (fcro=1) the trigger level interrupts, the receiver data available indication, the active rxrdy indica - tion and the overrun error indication will be delayed 3 rclks. statu s indicators (pe, fe, bi) will be delayed 3 rclks after the first byte has been received. for subsequently received bytes these indicators will be updated immediately after rdrbr goes inactive. timeout interrupt is delayed 8 rclks. 3. change and discharge time is determined by vol, voh and the external loading. 4.in fifo mode rc=425 ns (minimum) between reads of the receiver fifo and the status registers (interrupt identifica - tion register or line status register). 5. this delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active (see fifo interrupt mode operatione)
GM16C550 5 timing waveforms (all timings are referenced to valid 0 and valid) external clock input (8.0 mhz max.) at test points note 1: the 2.4v and 0.4v levels are the voltages that the inputs are driven to during ac testing. note 2: the 2.2v and 0.8v levels are the voltages at which the timing tests are made. baudout timing 2.4v xin 0.4v 2.2v 0.8v xh t xl t 2.4v 0.4v 2.2v 0.8v (note 1) (note 2) n xin out baud ) 2 ( ? out baud ) 1 ( ? out baud ) 3 ( ? out baud ) 3 n . n ( > ? bhd t bld t hw t lw t bhd t bhd t bhd t bld t bld t bld t hw t hw t cycles xin ) 2 n ( hw t - = lw t lw t lw t =2 xin ctles
GM16C550 6 timing waveforms (continued) write cycle *applicable only when ads is tied low. read cycle *applicable only when ads is tied low. ads a2,a1,a0 2 cs ,cs1,cs0 wr ,wr rd ,rd data d0 - d7 ads a2,a1,a0 2 cs ,cs1,c s0 wr ,wr rd ,rd data d0 - d7 ddis tads tas tah valid tcs tch twa* valid tscw* taw* tcsw* twc twr wc tds tdh valid data active active active tads tas tah valid tcs tch t ra* valid tcsr* tar* trcs* trc trd rc active active active valid data trdd trdd trvd thz or or
GM16C550 7 receiver ti ming transmitter timing modem comtrol timing note 1: see write cycle timing note 2: see read cycle timing serial out (sout) interrupt (thre) distr/di str (wr, thr) distr/distr (rd iir) start data(5 - parity stop(1 start tirs thr tsi tmr tsti tir distr/distr (wr mcr ) rts. dtr out1. out2 tmdo tmdo cts. dsr. dcd interrupt tsim trim trim tsim tsim distr/distr (rd msr) ri 8 clks sin receiver input data start tscd parity stop sample clk tsint trin active interrupt (data ready or rcvr err distr /dostr (read rec data buffer or rdlsr) rckk sample clk data bits(5 - 8)
GM16C550 8 timing waveforms (continued) ravr fifo first byte (this sets rdr) rcvr fifo byte other than th e first byte (rdr is already set) note 1: this is the reading of the last byte in the fifo note 2: if fcro =1, then tsint = 3 rclks. for a timeout tsint = 0 rclks . fifo or above trigger level fifo below trigger level lsi interrupt sin data (5 - 6) stop sample clock trigger level interrupt (fcr6,7 = 0.0) note 2 tsint trint trint active active rd, rd (rdls rd, rd (rdrbr) receiver ready (pin 29) fcro = 0 or fcro = 1 and fcro = 3 (mode 0) rd, rd (rdrbr) sin (first byte) stop active no te 1 sample clk rxrdy tsint note 2 trint sin sample clock timeout or trigger level interrupt note 2 tsint trint (fi fo below trigger level) tsint trint active active active previous byte read from fifo rd, rd (rdlsr) rd, rd (rdrbr) lsi interrupt top byte of fifo fifo at or above trigger level
GM16C550 9 timing waveforms (continued) note 1 : this si the reading of the last byte in the fifo note 2 : if fcro = 1, tsint = 3 rclks. receiver ready (pin 29) fcro = 0 or fcro = 1 and fcro = 1 (mode 1) rd, rd (rdrbr) sin (first stop active note 1 sample clk rxrdy tsint note 2 trint rcvr fifo byte other than first byte (rdr is already set) stop wr, wr (wrthr) sout txrdy byte 1 data parity start tsxa twxi transmitter ready (pin 24) fcro = 1 and fcr = 1 (mode 1) wr wr (wrthr) sout txrdy data byte 16 parity stop start twxi fifo full t sxa
GM16C550 10 internal block diagram receiver buffer register divior latch(ls) divisor latch(ms) transtmtter holding register line status register modem control register interrupt enable register interrupt id regiser modem status register line control register fifo control register receiver shift register receiver fifo transmitter fifo baud generator receiver timing & control s e l e c t receiver timing & control interrupt control logic mondem control logic s e l e c t transtmtter holding register data bus buffer selent & control logic power supply { (40) (20) gnd +5v (28) (27) (26) (12) (13) (14) (25) (35) (22) (21) (19) (23) (24) (16) (17) (29) sin rclk baudiut sou t rts dtr dsr dcd r 1 out1 out2 intr cts (32) (36) (33) (38) (39) (34) (31) (30) (37) (15) (9) (10) (11) cso cs1 cs2 asd mr rd rd wr wr ddis xin xout rxrdy txrdy d7 - d0 (1 - 8) internal data bus 18
GM16C550 11 pin descriptions the following describes the function of all uart pins. some of these desc riptions reference internal circuits. in the following descriptions, a low represents a logic 0 (0v nominal) and a high represents a logic 1 (+2.4v nominal). input signals chip select (cs0, cs1, 2 cs ) pins 12 - 14 : when cs0 and cs1 are high and 2 cs is low, the chip is selected. this enable communication between the uart and the cpu. the positive edge of an active address strobe signal latches the decoded chip select signals, completing chip selection. if ads is always low, valid chip selects should stabilize according to the csw parameter. read (rd, rd ), pins 22 and 21 : when rd is high or rd is low while the chip selected, the cpr can read status information or data from the selecte d uart register. note : only an active rd or rd input is required to transfer data from the uart during a read operation. therefore tie either the rd input permanently low or the rd input permanently high, when it is not used . write (w r, wr ), pin 19 and 18 : when wr is high or wr is low while the chip selected, the cpu can write control words or data into the selected uart register. note : only an active wr or wr input is requi red to transfer data to the uart during a write operation. therefore, tie either the wr input permanently low or the wr input permanently high, when it is not used . address strobe ( ads ), pin 25 : the positive edge o f an active address strobe ( ads ) signal latches the register select (a0, a1, a2) and chip select (cs0, cs1, cs2) signals. note : an active ads input is required when the register select (a0, a1, a2) signals are not stable for the durati on of a read or a write operation. if not required, tie the ads input permanently low. register select (a0, a1, a2), pins 26 - 28 : address signals connected to these 3 inputs select a uart register for the cpu to read from or write to during data transfer. a table of registers and addresses is shown below. note that the state of the divisor latch access bit (dlab), which is the most significant bit of the line control register, affects the selection of certain uart registers. the dlab must be set high by the system software to access the baud generator divisor latches. master reset (mr), pin 35 : when this input is high it clears all the registers (except the receiver buffer, transmitter holding, and divisor latches), and the control logic of the uart. the st ate of various output signals (sout, intr, 1 out , 2 out , rts , dtr) are affected by an active mr input (refer to table 1). this input is buffered with a ttl - compatible schmitt trigger with 0.5v typical hysteresis. receiver clock (rclk), pin 9 : this input is the 16 x baud rate clock for the receiver section of the chip. register address dlab a 2 a 1 a 0 register 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1 receiver buffer (read) transmitter holding register (write) interrupt enable interrupt identification (read) fifo control (write) line control modem control line status modem status scratch divisor latch (least significant byte) divisor latch (m ost significant byte) serial input (sin), pin 10 : serial data input from the communications link (peripheral device, modem, or data set). clear to send ( cts ), pin 36 : when low, this indicates that the modem or data set is ready to ex change data. the cts signal is a modem status input whose conditions can be tested by the cpu reading bit 4 (cts) of the modem status register. bit 4 is the complement of the cts signal. bit 0 (dcts) of the modem sta tus register indicates whether the cts input has changed state since the previous reading of the modem status register. cts has no effect on the transmitter. note : whenever the cts bit of the modem status register c hanges state, an interrupt is generated if the modem status interrupt is enabled . data set ready ( dsr ), pin 37 : when low, this indicates that the modem or data set is ready to establish the communications link with the uart. the dsr signal is a modem status input whose condition can be tested by the cpu reading bit 5 (dsr) of the modem status register. bit 5 is the complement of the dsr signal. bit 1 (ddsr) of the modem status register indicates wh ether the dsr input has changed state since the previous reading of the modem status register . note : whenever the dsr bit of the modem status register changes state, an interrupt is generated if the modem status interrupt is enabled. data carrier detect ( dcd ), pin 38 : when low, indicates that the data carrier has been detected by the modem or data set. the dcd signal is a modem status input whose condition can be tested by the register. bit 7 is the complement of the dcd signal. bit 3 (ddcd) of the modem status register indicates whether the dcd input has changed state since the previous reading of the modem status register. dcd has no ef fect on the receiver. note : whenever the dcd bit of the modem status register changes state, an interrupt is generated if the modem status interrupt is enabled. ring indicator ( ri ), pin 39: when low, this indicates that a telephone ri nging signal is received by the modem or data set. the ri signal is a modem status input whose condition can be tested by the cpu reading bit 6 ( ri ) of the modem status register. bit 6is the complement of the ri si gnal. bit 2 (teri) of the modem
GM16C550 12 status register indicates whether the ri input signal has changed from a low to a high state since the previous reading of the modem status register note : whenever the ri bit of the modem status regi - ster changes from a high to a low state, an inter - rupt is generated if the modem status interrupt is enabled. vcc, pin 40 : +5v supply. vss, pin 20 : ground(0v) reference. output signals data terminal ready ( dtr ), pin 33: when low, this informs the modem or data set that the uart is ready to establish communications link. the dtr output signal can be set to an active low by programming bit 0 (dtr) of the modem control registe r to high level. a master reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. request to send ( rts ), pin 32: when low, this informs the modem and data set that the uart is ready to exchange data. the rts output signal can be set to an active low by programming bit 1 (rts) of the modem control register. a master reset operation sets this signal to its inactive state. loop node operation holds this s ignal in its inactive state. output 1 ( 1 out ), pin 34: this user - designed out - put can be set to an active low by programming bit 2 (out1) of the modem control register to a high level. a master reset operation sets this signal to its ina ctive state. loop mode operation holds this signal to its inactive state. output 2 ( 2 out ), pin 31: this user - designated output can be set to an active low by programming bit 3 (out2) of the modem control register to a high level. a mast er reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal to its inactive state. txrdy, rxrdy, pin 24, 29: transmitter and receiver dma signaling is available through two pins (24 and 29). when operating in th e fifo mode, one of two types dma signaling per pin can be selected via fcr3, when operating as in the gm16c16450 mode., only dma mode 0 is allowed. mode 0 supports single transfer dma where a transfer is made between cpu bus cycles. mode 1 supports multi - transfer dma where multiple transfers ard made continuously until the rcvr fifo has been emptied or the xmit fifo has been filled. rxrdy mode 0: when in the gm16c450 mode (fcr0 = 0) or in the fifo mode (fcro = 1, rcr3 = 0) and there is at least 1 characte r in the rcvr fifo of rcvr holding register, the rxrdy pin (29) will be low active. once it is activated the rxrcy pin will go inactive when there are no more characters in the fifo of holding register. rxrdy mode 1: in the fifo mode (fcr0 = 1) when the f rc3 = 1 and the trigger level or the timeout has been reached , the rxrdy pin will go low active. once it is activated it will go inactive when there are no more characters in the fifo or holding register. txrdy mode 0: in the gm16c450 mode (fcr0 = 0) or i n the fifo mode (fcr = 1, fcr3 = 0) and there are no characters in the xmit fifo or xmit hold register, the txrdy pin(24) will be low active. once it is activated the txrdy pin will go inactive after the first character is loaded into the xmit fifo or hold ing register. txrdy mode 1 : in the fifo mode (fcr0 = 1) when fcr3 = 1 and there is at least one unfilled position in the xmit fifo, it will go low active. this pin will become inactive when the xmit fifo is completely full. driver disable (ddis), pin 23: this goes low whenever the cpu is reading data from the uart. it can disable or control the direction of a data bus transceiver between the cpu and the uart. baud out ( baudout ), pin 23: this is the 16x clock signal from the transmitter se ction of the uart. the clock rate is equal to the main reference oscillator frequency divided by the specified divisor in the baud generator divisor latches. the baudout may also be used for the receiver section by tying this output to the r clk input of the chip. interrupt (intr), pin 30: this pin goes high when - ever any one of the following interrupt types has an active high cognition and is enabled via the ier; receiver error flag; received data avail - able; timeout (fifo mode only); transm itter holding r e gister empty; and modem status, the intr signal is reset low upon the appropriate interrupt service or a master reset operation. serial output (sout), pin 11: composite serial data output to the communications link (peripheral. modem or da ta set). the sout signal is set to the marking (logic 1) state upon a master reset operation. input / output signals data (d7 - d0) bus, pin 1 - 8: this bus comprises eight tri - state input/output lines. the bus provides bi - directional communications between the uart and the cpu, data, control words. and status information are transferred via the d7 - d0 data bus. external clock input/output (xin, xout), pins 16 and 17: these two pins connect the main timing reference (crystal or signal clock) to the uart.
GM16C550 13 t able i. uart reset configuration note 1 : boldface bits are permanently low. note 2 : bits 7 - 4 are driven by the input signals. register / signal reset control reset state interrupt enable register interrupt identification register fifo control line control register modem control register line status register modem status register sout intr (rcvr e rrs) intr (rcvr data ready) intr (thre) intr (modem status changes) 2 out rts dtr 1 out rcvr fifo xmit fifo master reset master reset master reset master reset master reset master reset master reset master reset read lsr/mr read rbr/mr read iir/write thr/mr read msr/mr master reset master reset master reset master reset mr/rcr1 - fcr0/ fcr0 mr/rcr1 - fcr0/ fcr0 0000 0000 (note 1) 0000 0001 0000 0000 0000 0000 0000 0000 0110 00 00 xxxx 0000 (note 2) high low low low low high high high high all bits low all bits low
GM16C550 14 1 dlab = 1 divisor latch (ms) dlm bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 0 dlab = 1 divisor latch (ls) dll bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 7 scratch register scr bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 6 modem status register msr delta clear to send (dcts) delta data set ready (ddsr) trading edge ring indi cator (teri) delta data camer delect (ddcd) clear to send (cts) data set ready (dsr) ring indicator (ri) data camer detect (dcd) 5 line status register lsr data ready (dr) overrun error (oe) parity error (pe) framing error (fe) break interrupt (bi) tra nsmitter holding register (thre) transmitter empty (temt) error in rcbr fifo (note2) 4 modem control register mcr data terminal ready (dtr) request to send (rts) out1 out2 loop 0 0 0 3 line control register lcr word length select bit 0 (wls0) word length select bit 1 (wls1) number of stop bits (stb) parity enable (pen) even parity select (eps) stick parity set break divisor latch access bit (dla3) 2 fifo control register (write only) fcr fifo enable rcvr fifo reset xmit fifo reset dma mode sele ct reserved reserved rcvr trigger (lsb) rcvr trigger (msb) 1 interrupt enable register iir ? 0 ? if interrupt pending interrupt id bit (0) interrupt id bit (1) interrupt id bit (2) (note 2) 0 0 fifo 3 enabled (note 2) fifo 3 enabled (note 2) 1 dlab = 0 interrupt enable register ier enable received data available interupt (erbfi) enable transmitter holding register empty interrupt (etbei) enable receiver line status enable modem status interrupt (edssi) 0 0 0 0 0 dlab = 0 transm itter holding register (write only) thr data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 register address 0 dlab = 0 receiver buffer register (read only) rbr data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 table ii. summary of registe rs bit no. 0 1 2 3 4 5 6 7 note 1: bit 0 is the least significant bit seriously transmitted or received note 2:these bits are always 0 in the gm16c450 mode
GM16C550 15 registers the system programmer may be access any of the uart registers summarized in table ii via the cpu. these registers control uart operations including transmission and reception of data. each regi ster bit in table ii has its name and reset state shown. line control register the system programmer specifies the format of the asynchronous data communications exchange and set the divisor latch access bit via the line control register (lcr). the progra mmer can also read the contents of the line control register. the read capability simplifies system programming and eliminates the need for separate storage in system memory of the lcr. details on each bit follow : bit 0 and 1: these two bits specify the n umber of bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows. bit 1 bit 0 character length 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits bit 2: this bit specifies the number of stop bits transmitted and recei ved in each serial character. if bit 2 is a logic 0, one stop bit is generated in the transmitted data. if bit 2 is a logic 1 when a 5 - bit word length is selected via bits 0 and 1, one and a half stop bits are generated. if bit 2 is a logic 1 when either a 6 - , 7 - , or 8 - bit word length is selected, two stop bit are generated. the receiver checks the first stop bit only, regardless of the number of stop bit selected. bit 3: this bit is the parity enable bit. when bit 3 is a logic 1, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (the parity bit is used to produce an even or odd number of 1s when the data word bits and the parity bit are summed). bit 4: this bit is the even p arity select bit. when bit 3 is a logic 1 and bit 4 is a logic 0, and odd number of logic 1s is transmitt ed or checke d in the data word bits and parity bit. when bit 3is a logic 1 and it 4 is a logic 1, an even number of logic 1s is transmitted or checked. bit 5: this bit is the stick parity bit. when bit3, 4 and 5 are logic 1 the parity bit is transmitted and checked as a logic 0. if bit 3 and 5 are 1 and bit 4 is a logic 0 then the parity bit is transmitted and checked as a logic 1. if bit 5 is a logic 0 stick parity is disabled. bit 6: this bit is the break control bit. it causes a break condition to be transmitted to the received uart. when it is set to logic 1, the serial output (sout) is forced to the spacing (logic 0) state. the break is disabled b y setting bit 6 to a logic 0. the break control bit acts only on sout and has no effect on the transmitted logic. note : this feature enables the cpu to alert a terminal in during the break. the transmitter can be used as a character timer to accurately e stablish the break duration. a computer communications system. if the following sequence is followed. no erroneous or extraneous characters will be transmitted because of the break. 1. load on all os, pad character, in response to thre. 2. se t break after the next thre 3. wait for the transmitter to be idle. (temt = 1), and clear break when normal transmission has to be tired. during the bread, the transmitter can be used as a character timer to accurately establish the break duration. bit 7 : this bit is the divisor latch access bit (dlab). it must be set high (logic) to access the divisor latches of the baud generator during a read or write operation. it must be set low (logic 0) to access the receiver buffer, the transmitter holding registe r, or the interrupt enable register. typical clock circuits xin optional drive r optional clock output xout osc clock to baud gen. logic vcc external clock driver xin xout osc clock to baud gen. logic vcc crystal c1 c2 r p r 2
GM16C550 16 typical crystal oscillator network crystal r p r 2 c 1 c 2 3.1mhz 1.8mhz 1m w 1m w 1.5k 1.5k 10 - 30pf 10 - 30pf 40 - 60pf 40 - 60pf table iii. baud rates using 1.8432 mhz crystal desired baud rate decimal divisor used to generate 16 clock percent error difference between desired and actual 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 - - 0.0 26 0.058 ? ? ? ? 0.69 - - - - - - - 2.86
GM16C550 17 table iv. baud rates using 3.072 mhz crystal desired baud rate decimal divisor used to generate 16 clock percent error difference between desired and actual 50 75 110 134.5 150 300 600 12 00 1800 2000 2400 3600 4800 7200 9600 19200 38400 3840 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 - - 0.026 0.034 - - - - 0.312 - - 0.628 - 1.23 - - - table v. baud rate using 8mhz crystal desired baud rate decimal divisor used to gen erate 16 clock percent error difference between desired and actual 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 128000 256000 10000 6667 4545 3717 3333 1667 833 417 277 250 208 139 104 69 52 26 13 9 4 2 - 0.005 0. 010 0.013 0.010 0.020 0.040 0.080 0.080 - 0.160 0.080 0.160 0.644 0.160 0.160 0.160 0.790 2.344 2.344
GM16C550 18 interrupt reset control - reading the line status register rea ding the receiver buffer register or the fifo drops below the trigger level reading the receiver buffer register reading the iir register (if source of interrupt) or writing into the transmitter holding register reading the modem status register interr upt source none overrun error or parity error or framing error or break interrupt receiver data available or trigger level reached no characters have been removed from or input to the rcvr fifo during the last 4 char. times and there is at least 1 char. in it during this time transmitter holding register empty clear to send or data set ready or ring indicator or data carrier detect interrupt type none receiver line status received data available character timeout indication transmitter holding register empty modem status interrupt set and reset function priorit y level - highest second second third fourth bit 0 1 0 0 0 0 0 bit 1 0 1 0 0 1 0 interrupt identification bit 2 0 1 1 1 0 0 table vi.. interrupt control functions fifo mode only bit 3 0 0 0 1 0 0
GM16C550 19 programmable baud generator the uart contains a program mable baud generator that is capable of taking any clock input from 2 to 2 16 ? 1. 4mhz is the highest input clock frequency recommended when the divisor = 1. the output frequency of the baud generator is 16 the baud [divisor # = (frequency input) ? (baud rate 16)] two 8 - bit latches store the divisor in a 16 - bit binary format. these divisor latches must be loaded during initialization to ensure proper operation of the baud generator. upon loading either or the divisor latches, a 16 - bit baud counter is imme diately loaded. tables iii, iv and v provide decimal divisors to use with crystal frequencies of 1.8432 mhz 3.072mhz and 8 mhz, respectively. for baud rates of 38400 and below, the error obtain is minimal. the accuracy of the desired baud rate is dependen t on the crystal frequency chosen. using a divisor of zero is not recommended. line status register this register provides status information to the cpu concerning the data transfer. table ii shows the contents of the line status register. details on each bit follow. bit 0: this bit is the receiver data ready (dr) indicator. bit 0 is set to logic 1whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 1 is reset to a logic 0 by reading al l of the data in the receiver buffer register or the fifo. bit 1: this bit is the overrun error (oe) indicator. bit 1 indicates that data in the receiver buffer register was not read by the cpu before the next character was transferred into the receiver b uffer register, thereby destroying the previous character. the oe indicator is set to a logic 1 upon detection of an overrun condition and reset whenever the cpu reads the contents of the line status register if the fifo mode data continues to fill the fif o beyond the trigger level, an overrun error will occur only been completely received in the shift register. oe is indicated to the cpu as soon as it happens. the character on the shift register is overwritten, but is not transferred to the fifo. bit 2: t his bit is the parity error (pe) indicator. bit 2 indicates that the received data character does not have the correct even or odd parity. as selected by the even ? parity - select bit. the pe bit is set to a logic 1 upon detection of a parity error and is re set to a logic 0 whenever the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the when its associated character is at the top of the fifo. bit 3: this bit is the framing error (fe) indicator. bit3 indicates that the received character did not have a valid stop bit. bit 3is set to logic 1 whenever the stop bit following the last data bit or parity bit is detected as a logic 0 bit (spacing level). the fe indicator is reset wheneve r the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. the uart will try to resynchronize after a framing error. to do this it assumes that the framing error was due to the next start bit so it samples this ? start ? bit twice and then takes in the ? data ? . bit 4: this bit is the break interrupt (bi) indicator. bit 4 i s set to a logic 1 when ever the received data input is held in the spacing (logic) state for longer than a full word transmission time ( that is, the total time of start bit + data bits + parity + stop bits). the bi indicator is reset whenever the cpu read s the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. the next character transfer is enabled after sin goes to the marking state and receives the next valid start bit. note : bits 1 through 4 are the error conditions that produce a receiver line status interrupt wh enever any of the corresponding conditions are detected and the interrupt is enabled. bit 5: this bit is the transmitter holding register empty (thre) indicator. bit 5 indicates that the uart is ready to accept a new character for transmission. in additio n, this bit causes the uart to issue an interrupt to the cpu when the transmit holding register empty interrupt enable is set high. the thre bit is set to logic 1 when a character is transferred from the transmitter holding register into the transmitter sh ift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the cpu, in the fifo mode this bit is set when the xmit fifo is empty; it is cleared when at least 1 byte is written to the xmit fifo. bit 6: th is bit is the transmitter empty (temt) indicator. bit 6 is set to a logic 1 whenever the transmitter holding register (thr) and the trans - mitter shift register (tsr) are both empty. it is reset to a logic 0 whenever either the thr or tsr contains a data ch aracter. in the fifo mode this bit is set to one whenever the transmitter fifo and shift register are both empty. bit 7: in the gm16c450 mode this is a 0. in the fifo mode lsr7 is set when there is least one parity error, framing error or break indication in the fifo. lsr7 is cleared when the cpu reads the lsr, if there are no subsequent errors in the fifo. note: the line status register is intended for read op - erations only. writing to this register is not recom - mended as this operation is only used for factory testing. fifo control register this is a write only register at the same location as the iir (the iir is a read only register). this register is used to enable the fifos, set the rcvr fifo trigger level, and select the type of dma signaling.
GM16C550 20 bit 0: writing a 1 to fcr0 enables both the xmit and rcvr fifos. resetting fcr0 will clear all bytes in both fifos. when changing from fifo mode to gm16c450 mode and vice versa, data is automatically cleared from the fifos. this bit must be a 1 when other rcr bits are written to or they will not be programmed. bit 1: writing a 1 to fcr1 clears all bytes in the rcvr fifo and resets its counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self - clearing. bit 2: wri ting a 1 to fcr2 clears all bytes in the xmit fifo and resets its counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self - clearing. bit 3: setting fcr 3 to a 1 will cause the rxrdy and txrdy pins to change from mode 0 to mode 1 if fcr0 = 1 (see description of rxrdy and txrdy pins). bit4, 5: fcr4 to fcr5 are reserved for future use. bit6, 7: fcr6 to fcr7 are used to set the trigger level for the rcvr fifo interrupt. 7 6 rcvr fifo trigger level (bytes) 0 0 1 1 0 1 0 1 01 04 08 14 interrupt identification register in order to provide minimum software overhead during data character transfers, the uart prioritizes interrupts into four levels and records these in the interrupt identification register. the four levels of interrupt conditions in order of priority are receiver line status; received data ready; transmitter holding register empty; and modem status. when the cpu accesses the iir, the uart freezes all interrupts and indicates the highest priority pending interrupt to the cpu. while this cpu access is occurring, the uart records niw interrupts, but access is complete. table ii shows the contents of the iir. details on each bit follow: bit 0: this bit can be used in a prioritized interrupt environm ent to indicate whether an interrupt is pending. when bit 0 is a logic 0, an interrupt is pending and the iir contents may be used as a pointer to the appropriate interrupt service routine. when bit 0 is a logic 1, no interrupt is pending. bit 1 and 2: th ese two of the iir are used to identify highest priority interrupt pending as indicated in table vi. bit 3: in the gb16c450 mode this bit is 0. in the fifo mode this bit is set along with bit 2 when a timeout interrupt is pending. bit 4 and 5 : these tw o bits of the iir are always logic 0. bit 6 and 7: these two bits are set when fcr0 =1. interrupt enable register this register enables the five types of uart interrupts. each interrupt can individually activate the interrupt (intr) output signal. it is p ossible to totally disable the interrupt system by resetting bits 0 through 3 of the interrupt enable register (ier). similarly, setting bits of the ier register to a logic 1, enables the selected interrupt(s). disabling an interrupt prevents it from bein g indicated as active in the iir and from activating the intr output signal. all other system functions operate in their normal manner, including the setting of the line status and modem status registers. table ii shows the contents of the ier. details on each bit follow. bit 0: this bit enables the received data available interrupt (and timeout interrupts in the fifo mode) when set to logic1. bit 2: this bit enables the receiver line status interrupt when set to logic 1 bit 3: this bit enables the modem status interrupt when set to logic 1 bit 4 through 7: these four bits are always logic 0. modem control register this register controls the interface with the modem or data set (or peripheral device emulating a modem). the contents of the modem control r egister are indicated in table ii and are described below. bit 0: this bit controls the data terminal ready (dt r) output. when bit 0 is set to a logic 1, the dtr output is forced to a logic 0. when bit 0 is reset to a logic 0, the dtr output is forced to a logic 1. note: the dtr output of the uart may be applied to an eia inverting line driver (such as the gd751 - 88) to obtain the proper polarity input at the succ - eeding modem or data set. bit 1: this bit controls the request to send (r ts) output. bit 1 affects the rts output in a manner identical to that described above for bit 0. bit 2: this bit controls the output 1 (out1) signal , which is an auxillary user - designated output. bit 2 affects the out1 output in a manner identical to t hat described above for bit 0. bit 3: this bit controls the output 2(out2) signal, which is an auxillary user - designated output . bit 3 affects the out2 output in a manner identical to that described above for bit 0. bit 4: this bit provides a local loop back feature for diagnostic testing of the uart. when bit 4 is set to logic 1, the following occur ; the transmitter serial output (sout) is set to the marking (logic 1) state; the receiver serial input (sin) is disconnected; the output of the transmitter shift
GM16C550 21 register is ? looped back ? into the receiver shift register input; the four modem control inputs ( cts , rts , ri , and dcd ) are disconnected; and the four modem control output s ( dtr , rts , 1 out and 2 out ) are internally connected to the four modem control inputs, and the modem control output pins are forced to their inactive state (high). in the diagnostic mode, data that is transmitted is immediately received. this feature allows the processor to verify the transmitter and received - data paths of the uart. in the diagnostic mode, the receiver and transmitter interrupts are fully operational. their sources are external to the part. the modem control interrupts are also operational, but the interrupts sources are now the lower four bits or the modem control inputs. the interrupts are still controlled by the interrupt enable register. bits 5 through 7: these bits are permanently set to logic 0. modem status register this register provides the current state of the control lines from the modem (or peripheral device) to the cpu. in addition to this current - state information, four bits of the modem status registe r provide change information. these bits are set to a logic 1 whenever a control input from the modem changes state. they are reset to logic 0 whenever the cpu reads the modem status register. the contents of the modem status register are indicated in tab le ii and described below. bit 0: this bit is the delta clear to send (dcts) indicator. bit 0 indicates that the cts input to the chip has changed state since the last time it was read by the cpu. bit 1: this bit is the delta data set ready (ddsr) indicator. bit 1 indicates that the dsr input to the chip has changed state since the last tome it was read by the cpu. bit 2: this bit is the trailing edge of ring indicator (teri) detector. bit 2 indicates that the ri input to the chip has changed from a low to a high state. bit 3: this bit is the delta data carrier detect (ddcd) indicator. bit 3 indicates that the dcd input to the chip has changed state. note: whenever bit 0, 1, 2 or 3 is set to logic 1, a modem status interrupt is generated. bit 4: this bit is the complement of the clear to send ( cts ) input. if bit 4(loop) of the mcr is set to a 1, this bit is equivalent to rts in the mcr. bit 5: this bit is the complement of the data set ready ( dsr ) input. if bit 4 of the mcr is set to a 1, this bit is equivalent to dtr in the mcr. bit 6: this bit is the complement of the ring indicator. ( ri ) inpu t. if bit 4 of the mcr is set to a 1, this bit is equivalent to out1 in the mcr. bit 7: this bit is the complement of the data carrier detect(dcd) input. if but 4 of the mcr is set to a 1, this bit is equivalent to out2 in the mcr. scratchpad register thi s 8 - bit read/write register does not control the uart in anyway. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fcr0 = 1, ier0 =1) rcvr interrupts will occur as follows: a. the receive data available interrupts will be issued to the cpu when the fifo has reached its programmed trigger level; it will be cleared as soon as the fifo drops below its programmed trigger level. b . the iir receive data available indicate also occurs when the fifo trigger level is reached, and like the interrupt it is cleared when the fifo drops below the trigger level. c. the receiver line status interrupt (iir - 06), as before, has higher priority than received data available (iir - 04) interrupt. d. the data ready bit (lsr0)is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, r cvr fifo timeout interrupts will occur as follows: a. a fifo timeout interrupt will occur, if the following conditions exist: - at least one character is in the fifo - the most recent serial character received was longer than 4 continuous character t imes ago (if 2 stop bits are programmed the second one is included in this time delay). - the most recent cpu read if the fifo was longer than 4continuous character times age. this will cause a maximum character received to interrupt issued delay of 160ms a t 300baud with a 12 bit character. b. character times are calculated by using the rclk input for a clock signal (this makes the delay proportional to the baudrate). c. when a timeout interrupt has occurred it is cleared and the timer rest when the cpu re ads one character from the rcvr fifo. d. when a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are enabled (fcr0=1, ier=1 ) xmit interrupts will occur as follows: a. the transmitter holding register interrupt (02) occurs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is written to (1 to 16 characters may be written to the xmit fifo whi le servicing this interrupt) or the iir is read.
GM16C550 22 the transmitter fifo empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre = 1 and there have not been at least two bytes at the same time in th e transmit fifo, since the last thre = 1. the first transmitter interrupt affect changing fcr0 will be immediate, if it is enabled. character timeout and rcvr fifo trigger level interrupts have the same priority as the current received data available inte rrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt. fifo polled mode preration with fcrq = 1 resetting ier0, ier1, ier2, ier3 or all to zero puts the rcvr and mitter are controlled separately either one or both can be in the polled mode of operation. in this mode the user ? s program will check rcvr and xmitter status via the lsr. as stated previously: lsr0 will be set as long as there is one byte in the rcr fifo. lsr1 to lsr4 will specify which error(s) h as occurred. character error status is handled the same way when in the interrupt mode, the iir is not affected since ier2=0. lsr5 will indicate when the xmit fifo is empty. lsr6 will indicate that both the xmit fifo and shift register are empty. lsr7 will indicate whether there are any errors in the rcvr fifo. there is no trigger level reached or timeout condition indicated in the fifo polled mode, however, the rcvr and xmit fifos still fully capable of holding characters. application circuit latch address decoder data buffer system bus a 0 ? a 23 d 0 ? d 15 a 0 ? a 2 cpu GM16C550 reset cs2 ads rst dtr dsr dcd cts ri cs1 cs0 mr xtal1 xtal2 rclk sout sin intrpt txrdy ddis rxrdy +5 distr dost r distr dostr d 0 ? d 7 d 0 ? d 7 tor tcw eia drivers rs - 232 - c d interface d 0 - d 15

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